t | Magic Lantern Rescue
| t | Magic Lantern Rescue |
| ----------------------------
| | ---------------------------- |
| - Model ID: 0x417 200D
| | - Model ID: 0x412 M50 |
| - Camera model: Canon EOS 200D / Kiss X9
| | - Camera model: Canon EOS KISS M |
| - Firmware version: 1.0.1 / 5.0.2 62(31)
| | - Firmware version: 1.0.1 / 6.8.0 34(00) |
| - IMG naming: 100CANON/IMG_2342.JPG
| | - IMG naming: 100CANON/8733.JPG |
| | | - User PS: ??? ??? ??? |
| - Boot flags: FIR=0 BOOT=0 RAM=-1 UPD=-1
| | - Boot flags: FIR=0 BOOT=0 RAM=-1 UPD=-1 |
| - ROMBASEADDR: 0xE0040000
| | - ROMBASEADDR: 0xE0040000 |
| - boot_read/write_sector 1070c5 1071c1
| | |
| - 1018F3 Card init => 2
| | |
| - Dumping ROM0... 100%
| | |
| - MD5: 39a0d16fbda6b5e15112fc2b04c37426
| | |
| - Dumping ROM1... 100%
| | |
| - MD5: 711429a1a58d2a9387f6b0fae9db4953
| | |
| - No serial flash.
| | |
|
| | |
| CHDK CPU info for 0x417 200D
| | CHDK CPU info for 0x412 M50 |
| ------------------------------
| | ------------------------------ |
| ID 0x414FC091
| | ID 0x414FC091 |
| Revision 0x1 1
| | Revision 0x1 1 |
| Part 0xC09 3081
| | Part 0xC09 3081 |
| ARM Arch 0xF 15
| | ARM Arch 0xF 15 |
| Variant 0x4 4
| | Variant 0x4 4 |
| Implementor 0x41 65
| | Implementor 0x41 65 |
| Cache type 0x83338003
| | Cache type 0x83338003 |
| Icache min words/line 0x3 3 [8]
| | Icache min words/line 0x3 3 [8] |
| (zero) 0x0 0
| | (zero) 0x0 0 |
| L1 Icache policy 0x2 2
| | L1 Icache policy 0x2 2 |
| Dcache min words/line 0x3 3 [8]
| | Dcache min words/line 0x3 3 [8] |
| Exclusives Reservation Granule 0x3 3 [8]
| | Exclusives Reservation Granule 0x3 3 [8] |
| Cache Writeback Granule 0x3 3 [8]
| | Cache Writeback Granule 0x3 3 [8] |
| (zero) 0x0 0
| | (zero) 0x0 0 |
| (register format) 0x4 4
| | (register format) 0x4 4 |
| TCM type 0x00000000
| | TCM type 0x00000000 |
| (raw value) 0x0 0
| | (raw value) 0x0 0 |
| MPU type 0x414FC091
| | MPU type 0x414FC091 |
| S 0x1 1
| | S 0x1 1 |
| - 0x48 72
| | - 0x48 72 |
| Num of MPU regions 0xC0 192
| | Num of MPU regions 0xC0 192 |
| Multiprocessor ID 0x80000000
| | Multiprocessor ID 0x80000000 |
| (raw value) 0x80000000 -2147483648
| | (raw value) 0x80000000 -2147483648 |
| Processor feature 0 0x00001231
| | Processor feature 0 0x00001231 |
| ARM inst set 0x1 1
| | ARM inst set 0x1 1 |
| Thumb inst set 0x3 3
| | Thumb inst set 0x3 3 |
| Jazelle inst set 0x2 2
| | Jazelle inst set 0x2 2 |
| ThumbEE inst set 0x1 1
| | ThumbEE inst set 0x1 1 |
| - 0x0 0
| | - 0x0 0 |
| Processor feature 1 0x00000011
| | Processor feature 1 0x00000011 |
| Programmers' model 0x1 1
| | Programmers' model 0x1 1 |
| Security extensions 0x1 1
| | Security extensions 0x1 1 |
| Microcontr. prog model 0x0 0
| | Microcontr. prog model 0x0 0 |
| - 0x0 0
| | - 0x0 0 |
| Debug feature 0x00010444
| | Debug feature 0x00010444 |
| (raw value) 0x10444 66628
| | (raw value) 0x10444 66628 |
| Aux feature 0x00000000
| | Aux feature 0x00000000 |
| (raw value) 0x0 0
| | (raw value) 0x0 0 |
| Mem model feature 0 0x00100103
| | Mem model feature 0 0x00100103 |
| VMSA support 0x3 3
| | VMSA support 0x3 3 |
| PMSA support 0x0 0
| | PMSA support 0x0 0 |
| Cache coherence 0x1 1
| | Cache coherence 0x1 1 |
| Outer shareable 0x0 0
| | Outer shareable 0x0 0 |
| TCM support 0x0 0
| | TCM support 0x0 0 |
| Auxiliary registers 0x1 1
| | Auxiliary registers 0x1 1 |
| FCSE support 0x0 0
| | FCSE support 0x0 0 |
| - 0x0 0
| | - 0x0 0 |
| Mem model feature 1 0x20000000
| | Mem model feature 1 0x20000000 |
| L1 Harvard cache VA 0x0 0
| | L1 Harvard cache VA 0x0 0 |
| L1 unified cache VA 0x0 0
| | L1 unified cache VA 0x0 0 |
| L1 Harvard cache s/w 0x0 0
| | L1 Harvard cache s/w 0x0 0 |
| L1 unified cache s/w 0x0 0
| | L1 unified cache s/w 0x0 0 |
| L1 Harvard cache 0x0 0
| | L1 Harvard cache 0x0 0 |
| L1 unified cache 0x0 0
| | L1 unified cache 0x0 0 |
| L1 cache test & clean 0x0 0
| | L1 cache test & clean 0x0 0 |
| Branch predictor 0x2 2
| | Branch predictor 0x2 2 |
| Mem model feature 2 0x01230000
| | Mem model feature 2 0x01230000 |
| L1 Harvard fg prefetch 0x0 0
| | L1 Harvard fg prefetch 0x0 0 |
| L1 Harvard bg prefetch 0x0 0
| | L1 Harvard bg prefetch 0x0 0 |
| L1 Harvard range 0x0 0
| | L1 Harvard range 0x0 0 |
| Harvard TLB 0x0 0
| | Harvard TLB 0x0 0 |
| Unified TLB 0x3 3
| | Unified TLB 0x3 3 |
| Mem barrier 0x2 2
| | Mem barrier 0x2 2 |
| WFI stall 0x1 1
| | WFI stall 0x1 1 |
| HW access flag 0x0 0
| | HW access flag 0x0 0 |
| Mem model feature 3 0x00102111
| | Mem model feature 3 0x00102111 |
| Cache maintain MVA 0x1 1
| | Cache maintain MVA 0x1 1 |
| Cache maintain s/w 0x1 1
| | Cache maintain s/w 0x1 1 |
| BP maintain 0x1 1
| | BP maintain 0x1 1 |
| - 0x102 258
| | - 0x102 258 |
| Supersection support 0x0 0
| | Supersection support 0x0 0 |
| ISA feature 0 0x00101111
| | ISA feature 0 0x00101111 |
| Swap instrs 0x1 1
| | Swap instrs 0x1 1 |
| Bitcount instrs 0x1 1
| | Bitcount instrs 0x1 1 |
| Bitfield instrs 0x1 1
| | Bitfield instrs 0x1 1 |
| CmpBranch instrs 0x1 1
| | CmpBranch instrs 0x1 1 |
| Coproc instrs 0x0 0
| | Coproc instrs 0x0 0 |
| Debug instrs 0x1 1
| | Debug instrs 0x1 1 |
| Divide instrs 0x0 0
| | Divide instrs 0x0 0 |
| - 0x0 0
| | - 0x0 0 |
| ISA feature 1 0x13112111
| | ISA feature 1 0x13112111 |
| Endian instrs 0x1 1
| | Endian instrs 0x1 1 |
| Exception instrs 0x1 1
| | Exception instrs 0x1 1 |
| Exception AR instrs 0x1 1
| | Exception AR instrs 0x1 1 |
| Extend instrs 0x2 2
| | Extend instrs 0x2 2 |
| IfThen instrs 0x1 1
| | IfThen instrs 0x1 1 |
| Immediate instrs 0x1 1
| | Immediate instrs 0x1 1 |
| Interwork instrs 0x3 3
| | Interwork instrs 0x3 3 |
| Jazelle instrs 0x1 1
| | Jazelle instrs 0x1 1 |
| ISA feature 2 0x21232041
| | ISA feature 2 0x21232041 |
| LoadStore instrs 0x1 1
| | LoadStore instrs 0x1 1 |
| Memhint instrs 0x4 4
| | Memhint instrs 0x4 4 |
| MultiAccess Interruptible instructions 0x0 0
| | MultiAccess Interruptible instructions 0x0 0 |
| Mult instrs 0x2 2
| | Mult instrs 0x2 2 |
| MultS instrs 0x3 3
| | MultS instrs 0x3 3 |
| MultU instrs 0x2 2
| | MultU instrs 0x2 2 |
| PSR AR instrs 0x1 1
| | PSR AR instrs 0x1 1 |
| Reversal instrs 0x2 2
| | Reversal instrs 0x2 2 |
| ISA feature 3 0x11112131
| | ISA feature 3 0x11112131 |
| Saturate instrs 0x1 1
| | Saturate instrs 0x1 1 |
| SIMD instrs 0x3 3
| | SIMD instrs 0x3 3 |
| SVC instrs 0x1 1
| | SVC instrs 0x1 1 |
| SynchPrim instrs 0x2 2
| | SynchPrim instrs 0x2 2 |
| TabBranch instrs 0x1 1
| | TabBranch instrs 0x1 1 |
| ThumbCopy instrs 0x1 1
| | ThumbCopy instrs 0x1 1 |
| TrueNOP instrs 0x1 1
| | TrueNOP instrs 0x1 1 |
| T2 Exec Env instrs 0x1 1
| | T2 Exec Env instrs 0x1 1 |
| ISA feature 4 0x00011142
| | ISA feature 4 0x00011142 |
| Unprivileged instrs 0x2 2
| | Unprivileged instrs 0x2 2 |
| WithShifts instrs 0x4 4
| | WithShifts instrs 0x4 4 |
| Writeback instrs 0x1 1
| | Writeback instrs 0x1 1 |
| SMC instrs 0x1 1
| | SMC instrs 0x1 1 |
| Barrier instrs 0x1 1
| | Barrier instrs 0x1 1 |
| SynchPrim_instrs_frac 0x0 0
| | SynchPrim_instrs_frac 0x0 0 |
| PSR_M instrs 0x0 0
| | PSR_M instrs 0x0 0 |
| - 0x0 0
| | - 0x0 0 |
| ISA feature 5 0x00000000
| | ISA feature 5 0x00000000 |
| - 0x0 0
| | - 0x0 0 |
| Cache level ID 0x09200003
| | Cache level ID 0x09200003 |
| Cache type, level1 0x3 3 [Separate Icache, Dcache]
| | Cache type, level1 0x3 3 [Separate Icache, Dcache] |
| Cache type, level2 0x0 0 [no cache]
| | Cache type, level2 0x0 0 [no cache] |
| Cache type, level3 0x0 0 [no cache]
| | Cache type, level3 0x0 0 [no cache] |
| Cache type, level4 0x0 0 [no cache]
| | Cache type, level4 0x0 0 [no cache] |
| Cache type, level5 0x0 0 [no cache]
| | Cache type, level5 0x0 0 [no cache] |
| Cache type, level6 0x0 0 [no cache]
| | Cache type, level6 0x0 0 [no cache] |
| Cache type, level7 0x0 0 [no cache]
| | Cache type, level7 0x0 0 [no cache] |
| Cache type, level8 0x1 1 [Icache only]
| | Cache type, level8 0x1 1 [Icache only] |
| Level of coherency 0x1 1
| | Level of coherency 0x1 1 |
| Level of unification 0x1 1
| | Level of unification 0x1 1 |
| (zero) 0x0 0
| | (zero) 0x0 0 |
| Cache size ID reg (data, level0) 0x700FE019
| | Cache size ID reg (data, level0) 0x700FE019 |
| Line size in words 0x1 1 [8]
| | Line size in words 0x1 1 [8] |
| Associativity 0x3 3 [4]
| | Associativity 0x3 3 [4] |
| Number of sets 0x7F 127 [128]
| | Number of sets 0x7F 127 [128] |
| Write allocation 0x1 1
| | Write allocation 0x1 1 |
| Read allocation 0x1 1
| | Read allocation 0x1 1 |
| Write back 0x1 1
| | Write back 0x1 1 |
| Write through 0x0 0
| | Write through 0x0 0 |
| Cache size ID reg (inst, level0) 0x200FE019
| | Cache size ID reg (inst, level0) 0x200FE019 |
| Line size in words 0x1 1 [8]
| | Line size in words 0x1 1 [8] |
| Associativity 0x3 3 [4]
| | Associativity 0x3 3 [4] |
| Number of sets 0x7F 127 [128]
| | Number of sets 0x7F 127 [128] |
| Write allocation 0x0 0
| | Write allocation 0x0 0 |
| Read allocation 0x1 1
| | Read allocation 0x1 1 |
| Write back 0x0 0
| | Write back 0x0 0 |
| Write through 0x0 0
| | Write through 0x0 0 |
| SCTLR 0x48C5187D
| | SCTLR 0x40C5187D |
| MPU Enable 0x1 1
| | MPU Enable 0x1 1 |
| Strict Align 0x0 0
| | Strict Align 0x0 0 |
| L1 DCache Enable 0x1 1
| | L1 DCache Enable 0x1 1 |
| - (SBO) 0xF 15
| | - (SBO) 0xF 15 |
| - (SBZ) 0x0 0
| | - (SBZ) 0x0 0 |
| Branch Pred Enable 0x1 1
| | Branch Pred Enable 0x1 1 |
| L1 ICache Enable 0x1 1
| | L1 ICache Enable 0x1 1 |
| High Vectors 0x0 0
| | High Vectors 0x0 0 |
| Round Robin 0x0 0
| | Round Robin 0x0 0 |
| - (SBZ) 0x0 0
| | - (SBZ) 0x0 0 |
| - (SBO) 0x1 1
| | - (SBO) 0x1 1 |
| MPU background reg 0x0 0
| | MPU background reg 0x0 0 |
| - (SBO) 0x1 1
| | - (SBO) 0x1 1 |
| Div0 exception 0x0 0
| | Div0 exception 0x0 0 |
| - (SBZ) 0x0 0
| | - (SBZ) 0x0 0 |
| FIQ Enable 0x0 0
| | FIQ Enable 0x0 0 |
| - (SBO) 0x3 3
| | - (SBO) 0x3 3 |
| VIC 0x0 0
| | VIC 0x0 0 |
| CPSR E bit 0x0 0
| | CPSR E bit 0x0 0 |
| - (SBZ) 0x0 0
| | - (SBZ) 0x0 0 |
| NMFI 0x1 1
| | NMFI 0x0 0 |
| TRE 0x0 0
| | TRE 0x0 0 |
| AFE 0x0 0
| | AFE 0x0 0 |
| Thumb exceptions 0x1 1
| | Thumb exceptions 0x1 1 |
| Big endian 0x0 0
| | Big endian 0x0 0 |
| ACTLR 0x00000045
| | ACTLR 0x00000045 |
| (raw value) 0x45 69
| | (raw value) 0x45 69 |
| ACTLR2 0x00000201
| | ACTLR2 0x00000701 |
| (raw value) 0x201 513
| | (raw value) 0x701 1793 |
| CPACR 0xC0000000
| | CPACR 0xC0000000 |
| (raw value) 0xC0000000 -1073741824
| | (raw value) 0xC0000000 -1073741824 |
| DBGDIDR 0x35137041
| | DBGDIDR 0x35137041 |
| Revision 0x1 1
| | Revision 0x1 1 |
| Variant 0x4 4
| | Variant 0x4 4 |
| - (RAZ) 0x70 112
| | - (RAZ) 0x70 112 |
| Version 0x3 3 [v7 full]
| | Version 0x3 3 [v7 full] |
| Context 0x1 1 [2]
| | Context 0x1 1 [2] |
| BRP 0x5 5 [6]
| | BRP 0x5 5 [6] |
| WRP 0x3 3 [4]
| | WRP 0x3 3 [4] |
| DBGDRAR 0x00000000
| | DBGDRAR 0x00000000 |
| Valid 0x0 0
| | Valid 0x0 0 |
| - (UNK) 0x0 0
| | - (UNK) 0x0 0 |
| Address 0x0 0 [0x00000000]
| | Address 0x0 0 [0x00000000] |
| DBGDSAR 0x00030000
| | DBGDSAR 0x00030000 |
| Valid 0x0 0
| | Valid 0x0 0 |
| - (UNK) 0x0 0
| | - (UNK) 0x0 0 |
| Address 0x30 48 [0x00030000]
| | Address 0x30 48 [0x00030000] |
| DBGDSCR 0x03000002
| | DBGDSCR 0x03000002 |
| HALTED 0x0 0
| | HALTED 0x0 0 |
| RESTARTED 0x1 1
| | RESTARTED 0x1 1 |
| MOE 0x0 0
| | MOE 0x0 0 |
| SDABORT_l 0x0 0
| | SDABORT_l 0x0 0 |
| ADABORT_l 0x0 0
| | ADABORT_l 0x0 0 |
| UND_l 0x0 0
| | UND_l 0x0 0 |
| FS 0x0 0
| | FS 0x0 0 |
| DBGack 0x0 0
| | DBGack 0x0 0 |
| INTdis 0x0 0
| | INTdis 0x0 0 |
| UDCCdis 0x0 0
| | UDCCdis 0x0 0 |
| ITRen 0x0 0
| | ITRen 0x0 0 |
| HDBGen 0x0 0
| | HDBGen 0x0 0 |
| MDBGen 0x0 0
| | MDBGen 0x0 0 |
| SPIDdis 0x0 0
| | SPIDdis 0x0 0 |
| SPNIDdis 0x0 0
| | SPNIDdis 0x0 0 |
| NS 0x0 0
| | NS 0x0 0 |
| ADAdiscard 0x0 0
| | ADAdiscard 0x0 0 |
| ExtDCCmode 0x0 0
| | ExtDCCmode 0x0 0 |
| - (SBZ) 0x0 0
| | - (SBZ) 0x0 0 |
| InstrCompl_l 0x1 1
| | InstrCompl_l 0x1 1 |
| PipeAdv 0x1 1
| | PipeAdv 0x1 1 |
| TXfull_l 0x0 0
| | TXfull_l 0x0 0 |
| RXfull_l 0x0 0
| | RXfull_l 0x0 0 |
| - (SBZ) 0x0 0
| | - (SBZ) 0x0 0 |
| TXfull 0x0 0
| | TXfull 0x0 0 |
| RXfull 0x0 0
| | RXfull 0x0 0 |
| - (SBZ) 0x0 0
| | - (SBZ) 0x0 0 |
|
| | |
| - DONE! | | - DONE! |